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| SL74HC138 1-of-8 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS The SL74HC138 is identical in pinout to the LS/ALS138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC138 decodes a three-bit Address to one-of-eight activelow outputs. This device features three Chip Select inputs, two activelow and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC138N Plastic SL74HC138D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs CS1 CS2 CS3 XXH XHX LXX H H H H H H H H L L L L L L L L L L L L L L L L A2 A1 A0 XXX XXX XXX LLL LLH LHL LHH HLL HLH HHL HHH Outputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H HHHHH H H H HHHHH H H H HHHHH L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H H H H H H H H H PIN 16 =VCC PIN 8 = GND LHHH HLHH HHLH HHHL H = high level (steady state) L = low level (steady state) X = don't care SLS System Logic Semiconductor SL74HC138 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 2) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions m be taken to avoid applications of any voltage higher than maximum rated ust voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL74HC138 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 4.0 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 40 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0A SLS System Logic Semiconductor SL74HC138 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 4) Maximum Propagation Delay , CS1 to Output Y (Figures 2 and 4) Maximum Propagation Delay , CS2 or CS3 to Output Y (Figures 3 and 4) Maximum Output Transition Time, Any Output (Figures 2 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 135 27 23 110 22 19 120 24 20 75 15 13 10 85C 170 34 29 140 28 24 150 30 26 95 19 16 10 125C 205 41 35 165 33 28 180 36 31 110 22 19 10 Unit ns tPLH, t PHL ns tPLH, t PHL ns tTLH, t THL ns CIN pF Typical @25C,VCC=5.0 V 55 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC138 Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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